Computers , 1990 , 39 : 564 - 571 . 20 jiang j h . alternating - complementary locator and its use for error location in dual - modular redundancy with comparison structure 隨著要求高可用性和高可維護(hù)性的應(yīng)用需求的增長,重試結(jié)構(gòu)因其硬件開銷低而獲得了廣泛應(yīng)用。
To tolerate faults , the techniques rely on redundant implementations , which are n - modular redundancy for building fault - tolerant hardware and n - version programming or recovery blocks method for building fault - tolerant software 容錯(cuò)的技術(shù)在于采用冗余工具,也就是采用n模塊冗余構(gòu)造容錯(cuò)硬件,采用n版本編程或恢復(fù)塊方法構(gòu)造容錯(cuò)軟件。
To solve this problem , this paper presents a novel dual modular redundancy structure using complementary logic - alternating - complementary logic cl - acl switching mode . during error - free operation , the cl - acl structure operates by complementary logic mode . after an error is detected , it retries by alternating logic mode 在低電源電壓2 . 2v或更低或在0 . 1 m m vlsi工藝條件下,具有大于10 mev能級(jí)的宇宙中子流以高達(dá)20中子平方厘米小時(shí)到達(dá)地球表面時(shí)所引起的電路的隨機(jī)差錯(cuò)率將是難以接受的。